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This sounds rather complex—the instruction must be decoded from in P during t1 and from the IR during t2.
Fortunately, we can simplify this by using a transparent register for the IR.
This timing diagram shows how t2 is inserted for the Program Memory accesses, and what data is on the various buses at what time.
The instructions shown are: (No r/w) no memory access, (M rd) Data Memory read, (P rd) Program Memory read, (M wr) Data Memory write, (P wr) Program Memory write, (M mod) Data Memory modify and (P mod) Program Memory modify.
When a bus on the timing diagram shows a midline value, the bus's output is undefined or its input value is unused.